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STM8S105K6U3C View Datasheet(PDF) - STMicroelectronics

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STM8S105K6U3C Datasheet PDF : 127 Pages
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Electrical characteristics
(4) Configured by the REGAH bit in the CLK_ICKR register.
(5) Configured by the AHALT bit in the FLASH_CR1 register.
(6) Plus 1 LSI clock depending on synchronization.
STM8S105xx
10.3.2.6 Total current consumption and timing in forced reset state
Symbol
Table 30: Total current consumption and timing in forced reset state
Parameter
Conditions
Typ
Max(1) Unit
IDD(R)
Supply current in reset
state(2)
VDD = 5 V
VDD = 3.3 V
500
μA
400
tRESETBL
Reset pin release to
vector fetch
150
μs
(1) Data guaranteed by design, not tested in production.
(2) Characterized with all I/Os tied to VSS.
10.3.2.7 Current consumption of on-chip peripherals
Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz.
Table 31: Peripheral current consumption
Symbol
Parameter
Typ.
IDD(TIM1)
TIM1 supply current(1)
230
IDD(TIM2)
TIM2 supply current (1)
115
IDD(TIM3)
TIM3 timer supply current (1)
90
IDD(TIM4)
TIM4 timer supply current (1)
30
IDD(UART2)
UART2 supply current(2)
110
IDD(SPI)
SPI supply current (2)
45
Unit
µA
72/127
DocID14771 Rev 9

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