STM8S105xx
Electrical characteristics
Symbol
th(SO) (1)
th(MO) (1)
Parameter
Data output
hold time
Conditions
Slave mode
(after enable edge)
Master mode
(after enable edge)
Min
Max Unit
28
ns
12
ns
(1) Values based on design simulation and/or characterization results, and not tested in
production.
(2) Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
(3) Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
Figure 41: SPI timing diagram - slave mode and CPHA = 0
NSS input
tSU(NSS)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
MISO
OUT P UT
tsu(SI)
MOSI
I NPUT
tc(SCK)
tv(SO)
MS B O UT
M SB IN
th(SI)
th(SO)
BI T6 OUT
B I T1 IN
th(NSS)
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
LSB IN
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