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STM8S10XS6U3ATR View Datasheet(PDF) - STMicroelectronics

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STM8S10XS6U3ATR Datasheet PDF : 121 Pages
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STM8S105x4/6
Electrical characteristics
10.3.6 I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 37. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Vhys
Rpu
tR, tF
tR, tF
Ilkg
Input low level voltage
Input high level voltage
Hysteresis(1)
Pull-up resistor
Rise and fall time
(10% - 90%)
Rise and fall time
(10% - 90%)
Digital input leakage
current
VDD = 5 V
VDD = 5 V, VIN = VSS
Fast I/Os
Load = 50 pF
Standard and high sink I/Os
Load = 50 pF
Fast I/Os
Load = 20 pF
Standard and high sink I/Os
Load = 20 pF
-0.3 V
0.7 x VDD
-
30
-
-
-
-
VSS VIN VDD
-
-
0.3 x VDD
V
-
VDD + 0.3 V
700
-
mV
55
80
kï—
-
35(2)
ns
-
125(2)
-
20(2)
ns
-
50(2)
-
±1(3)
µA
Ilkg ana
Analog input leakage
current
VSS VIN VDD
-
Ilkg(inj)
Leakage current in
adjacent I/O
Injection current ±4 mA
-
-
±250(3)
nA
-
±1(3)
µA
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
2. Data guaranteed by design.
3. Data based on characterization results, not tested in production
DocID14771 Rev 15
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