PIC16(L)F1503
TABLE 28-4: I/O PORTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
VIL
Input Low Voltage
I/O PORT:
D030
with TTL buffer
—
D030A
—
D031
with Schmitt Trigger buffer
—
with I2C™ levels
—
with SMbus levels
—
D032
MCLR
—
VIH
Input High Voltage
I/O PORT:
—
0.8
V 4.5V VDD 5.5V
—
0.15 VDD V 1.8V VDD 4.5V
—
0.2 VDD V 2.0V VDD 5.5V
—
0.3 VDD V
—
0.8
V 2.7V VDD 5.5V
—
0.2 VDD V
D040
D040A
D041
D042
IIL
D060
with TTL buffer
2.0
—
0.25 VDD +
—
0.8
with Schmitt Trigger buffer 0.8 VDD
—
with I2C™ levels
0.7 VDD
—
with SMbus levels
2.1
—
MCLR
0.8 VDD
—
Input Leakage Current(1)
I/O Ports
—
±5
—
—
—
—
—
—
± 125
V 4.5V VDD 5.5V
V 1.8V VDD 4.5V
V 2.0V VDD 5.5V
V
V 2.7V VDD 5.5V
V
nA VSS VPIN VDD,
Pin at high-impedance, 85°C
D061
MCLR(2)
—
±5
± 1000 nA VSS VPIN VDD,
Pin at high-impedance, 125°C
—
± 50
± 200
nA VSS VPIN VDD,
Pin at high-impedance, 85°C
D070*
IPUR
Weak Pull-up Current
VOL
D080
Output Low Voltage
I/O Ports
VOH
D090
Output High Voltage
I/O Ports
25
100
25
140
—
—
VDD - 0.7
—
200
A VDD = 3.3V, VPIN = VSS
300
A VDD = 5.0V, VPIN = VSS
IOL = 8 mA, VDD = 5V
0.6
V IOL = 6 mA, VDD = 3.3V
IOL = 1.8 mA, VDD = 1.8V
IOH = 3.5 mA, VDD = 5V
—
V IOH = 3 mA, VDD = 3.3V
IOH = 1 mA, VDD = 1.8V
Capacitive Loading Specifications on Output Pins
D101A* CIO
All I/O pins
—
—
50
pF
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
DS40001607D-page 274
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