PIC16(L)F1503
REGISTER 7-7:
U-0
—
bit 7
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
CLC2IF
R/W-0/0
CLC1IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘0’
CLC2IF: Configurable Logic Block 2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
CLC1IF: Configurable Logic Block 1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
DS40001607D-page 70
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