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PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

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Description
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PIC32MX230F128L-I/PF Datasheet PDF : 382 Pages
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15.1 Control Registers
TABLE 15-1: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 5 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 —
2000 IC1CON(1)
15:0 ON
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV ICBNE
ICM<2:0>
2010
IC1BUF
31:16
15:0
IC1BUF<31:0>
2200
IC2CON(1)
31:16
15:0
ON
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
2210
IC2BUF
31:16
15:0
IC2BUF<31:0>
2400
IC3CON(1)
31:16
15:0
ON
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
2410
IC3BUF
31:16
15:0
IC3BUF<31:0>
2600
IC4CON(1)
31:16
15:0
ON
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
2610
IC4BUF
31:16
15:0
IC4BUF<31:0>
2800
IC5CON(1)
31:16
15:0
ON
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
2810
IC5BUF
31:16
15:0
IC5BUF<31:0>
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for more
information.
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx

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