TABLE 17-1: SPI1 THROUGH SPI4 REGISTER MAP (CONTINUED)
Bits
31/15
30/14 29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
5C40 SPI3CON2
15:0
SPI
SGNEXT
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
IGNROV
IGNTUR
AUDEN
—
—
—
AUD
MONO
—
AUDMOD<1:0> 0000
5E00
SPI4CON(2)
31:16
15:0
FRMEN
ON
FRMSYNC FRMPOL
—
SIDL
MSSEN
DISSDO
FRMSYPW
FRMCNT<2:0>
MODE32 MODE16 SMP
CKE
MCLKSEL
SSEN
—
CKP
—
—
MSTEN DISSDI
—
—
STXISEL<1:0>
SPIFE ENHBUF 0000
SRXISEL<1:0> 0000
5E10
SPI4STAT(2)
31:16
15:0
—
—
—
—
—
RXBUFELM<4:0>
—
—
—
TXBUFELM<4:0>
0000
— FRMERR SPIBUSY
—
—
SPITUR SRMT SPIROV SPIRBE
—
SPITBE
—
SPITBF SPIRBF 19EB
5E20
SPI4BUF(2)
31:16
15:0
DATA<31:0>
0000
0000
5E30
SPI4BRG(2)
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
—
—
BRG<8:0>
0000
31:16 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
5E40 SPI4CON2(2) 15:0
SPI
SGNEXT
—
—
FRM
ERREN
SPI
ROVEN
SPI
TUREN
IGNROV
IGNTUR
AUDEN
—
—
—
AUD
MONO
—
AUDMOD<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
2:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV
Registers” for more information.
This register is only available on 100-pin devices.