PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 24-1: CMxCON: COMPARATOR CONTROL REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

31:24

U-0

—

U-0

U-0

U-0

U-0

—

—

—

—

U-0

—

23:16

U-0

—

U-0

U-0

U-0

U-0

—

—

—

—

U-0

—

15:8

R/W-0

ON(1)

R/W-0

R/W-0

U-0

COE

CPOL(2)

—

U-0

—

U-0

—

7:0

R/W-1

R/W-1

EVPOL<1:0>

U-0

R/W-0

U-0

—

CREF

—

U-0

—

Bit

Bit

25/17/9/1 24/16/8/0

U-0

U-0

—

—

U-0

U-0

—

—

U-0

R-0

—

COUT

R/W-1

R/W-1

CCH<1:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Comparator ON bit(1)

1 = Module is enabled. Setting this bit does not affect the other bits in this register

0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this

register

bit 14 COE: Comparator Output Enable bit

1 = Comparator output is driven on the output CxOUT pin

0 = Comparator output is not driven on the output CxOUT pin

bit 13 CPOL: Comparator Output Inversion bit(2)

1 = Output is inverted

0 = Output is not inverted

bit 12-9 Unimplemented: Read as ‘0’

bit 8

COUT: Comparator Output bit

1 = Output of the Comparator is a ‘1’

0 = Output of the Comparator is a ‘0’

bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits

11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output

10 = Comparator interrupt is generated on a high-to-low transition of the comparator output

01 = Comparator interrupt is generated on a low-to-high transition of the comparator output

00 = Comparator interrupt generation is disabled

bit 5

Unimplemented: Read as ‘0’

bit 4

CREF: Comparator Positive Input Configure bit

1 = Comparator non-inverting input is connected to the internal CVREF

0 = Comparator non-inverting input is connected to the CXINA pin

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator

11 = Comparator inverting input is connected to the IVREF

10 = Comparator inverting input is connected to the CxIND pin

01 = Comparator inverting input is connected to the CxINC pin

00 = Comparator inverting input is connected to the CxINB pin

Note 1:

2:

When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an

interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 273

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