26.1 Control Registers
TABLE 26-1: CTMU REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1 16/0
A200
CTMUCON
31:16
15:0
EDG1MOD
ON
EDG1POL
— CTMUSIDL
EDG1SEL<3:0>
EDG2STAT EDG1STAT EDG2MOD EDG2POL
TGEN EDGEN EDGSEQEN IDISSEN CTTRIG
EDG2SEL<3:0>
ITRIM<5:0>
—
—
IRNG<1:0>
0000
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for
more information.