PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

TABLE 32-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Standard Operating Conditions: 2.3V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

Parameter

No.

Typical(2)

Max.

Units

Conditions

Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1)

MDC34a

9.5

24

mA

50 MHz

Note 1: The test conditions for IIDLE current measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by

external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin

• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8

• CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1

• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared

• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled

• All I/O pins are configured as inputs and pulled to VSS

• MCLR = VDD

• RTCC and JTAG are disabled

2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

TABLE 32-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

Param.

No.

Typical(2)

Max.

Units

Conditions

Power-Down Current (IPD) (Note 1)

MDC40k 50

150

A

MDC40n 250

650

A

-40°C

+85°C

Base Power-Down Current

Module Differential Current

MDC41e

MDC42e

MDC43d

Note 1:

2:

3:

4:

15

55

A

3.6V

Watchdog Timer Current: IWDT (Note 3)

34

55

A

3.6V

RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)

1100

1800

A

3.6V

ADC: IADC (Notes 3,4)

The test conditions for IPD current measurements are as follows:

• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by

external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)

• OSC2/CLKO is configured as an I/O input pin

• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8

• CPU is in Sleep mode, and SRAM data memory Wait states = 1

• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set

• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled

• All I/O pins are configured as inputs and pulled to VSS

• MCLR = VDD

• RTCC and JTAG are disabled

Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

The  current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.

 2014-2017 Microchip Technology Inc.

DS60001290E-page 355

Share Link: