STLC5460 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5460 Datasheet PDF : 54 Pages
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STLC5460
Second Case CM = 0 (Bit of Command Register).
The auxiliary Memory is selected.
PCM
DT6
DT5
DT4
DT3
DT2
DT1
DT0
-
MON
TX
-
M0
G2
G1
G0
PCM Bit is not significant. The other bits are relevant only if multiplex is GCI (See bits of Multiplex Con-
figuration Register : GCI M0 and/or GCI M1).
MON
Command/Indicate
MON = 0. The channel is Command/Indicate
MON = 1. The channel is MON channel.
TX
Transmitter
TX = 1. The transmit channel is selected.
TX = 0. The receive channel is selected.
M0
Multiplex 0.
M0 = 0. The GCI multiplex 0 is selected.
M0 = 1. The GCI multiplex 1 is selected.
G2/G0
GCI 0/2
One of eight GCI channels of the multiplex selected (one GCI channel is
constituted by five sub-channels : B1, B2, D, C/I and MON).
If Multiplex is not GCI, the GCI channels are not validated. The 32 Time Slots of the multiplex can be
used for switching.
STATUS REGISTER (STATUS)
7
0
BID
BUSY PRSR MONR MONT
CIR
EXT
INS
After Reset 00 (H)
Each bit of this register is read only, except BID (bit) which can be written and read by the microproces-
sor.
BID
Bi-directional Switching.
BID = 1. two connection paths are established with the same µp instruction.
The µp writes successively into three register: Command Register, Source Register
and the Destination register lastly, when the Destination register has been written a
write command memory starts to set up the connection required by the µp.
The same information is used to establish a symmetrical connection:
Source register and Destination register are swapped, and so are the SS0/1 and
DS0/1 bit of Command Register.
BID = 0: one connection path is established.
The µp writes successively into three register: Command register, Source register
and Destination register lastly, when the Destination register has been written a write
command memory start to set up the connection required by the µp.
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