ZPSD302B-90JI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD302B-90JI Datasheet PDF : 85 Pages
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PSD3XX Family
10.
I/O Port
Functions
(cont.)
10.3 Port B (PB0-PB7)
The control registers of Port B are located in CSIOPORT space; see Table 5A and 5B.
10.3.1 Port B (PB0-PB7) in Multiplexed Address/Data Mode
Each pin of Port B can be individually configured. The following table summarizes what the
control registers (in CSIOPORT space) for Port B do:
Register Name
0 Value
Port B Pin Register
Port B Direction Register
Port B Data Register
Sampled logic level
at pin = ‘0’
Pin is configured
as input
Data in DFF = ‘0’
NOTE: 1. Default value is the value after reset.
1 Value
Sampled logic level
at pin = ‘1’
Pin is configured
as output
Data in DFF = ‘1’
Default
Value
(Note 1)
X
0
0
MCU I/O Mode
The default configuration of Port B is MCU I/O. In this mode, every pin can be set
t(s) (at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR
FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s
c data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the
u pin. The contents of the Pin Register indicate the true state of the PSD driving the pin
rod through the DFF or an external source driving the pin. Pins can be configured as CMOS
or open-drain using ST’s PSDsoft software. Open-drain pins require external pull-up
P resistors.
lete Chip Select Output
Alternatively, each bit of Port B can be configured to provide a chip-select output signal
so from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is
b not limited to chip selects only; they can be used for generic combinatorial logic as well.
O Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7
Obsolete Product(s) - signals is comprised of two product terms.
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