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STM8S207M6T3BTR View Datasheet(PDF) - STMicroelectronics

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Description
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STM8S207M6T3BTR Datasheet PDF : 103 Pages
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Electrical characteristics
Figure 37. SPI timing diagram - slave mode and CPHA = 0
STM8S207xx, STM8S208xx
NSS input
tSU(NSS)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
MISO
OUT P UT
tsu(SI)
MOSI
I NPUT
tc(SCK)
tv(SO)
MS B O UT
M SB IN
th(SI)
th(SO)
BI T6 OUT
B I T1 IN
Figure 38. SPI timing diagram - slave mode and CPHA = 1(1)
th(NSS)
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
LSB IN
ai14134
NSS input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
MISO
OUT P UT
MOSI
I NPUT
ta(SO)
tsu(SI)
tc(SCK)
tv(SO)
MS B O UT
th(SI)
M SB IN
th(SO)
BI T6 OUT
B I T1 IN
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
th(NSS)
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
LSB IN
ai14135
78/103
Doc ID 14733 Rev 12

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