DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Power Up and Reset Sequence—Intel® Quark SoC X1000

Figure 19. RTC Power Well Timing Diagrams

Initial

Power Up

State G3

Insert coin-cell battery

VCCRTC_3P3

RTCRST_B

32kHz Oscillator [int]

t1 [ext]

t2

Oscillator Start-Up

Clock Valid

Table 62.

9.2.3

RTC Power Well Timing Parameters

Parameter

Description

Min

Max

Units

Notes

t1

VCCRTC_3P3 to RTCRST#

deassertion

9

N/A

ms

1

t2

Oscillator Startup Time

TBD

TBD

s

2,3

Notes:

1.

This delay is typically created from an RC circuit.

2.

The oscillator startup times are component and design specific. A crystal oscillator can take as long as

2 s to reach a large enough voltage swing. Whereas, a silicon oscillator can have startups times

<10 ms.

Power-Up Sequence without G2/G3: No Coin-Cell Battery

This sequence must be adhered to in cases where one of the following conditions apply:

1. The system does not implement an RTC battery (coin cell) or a main battery.

2. The coin cell is drained with no main or a dead main battery.

3. No coin cell implemented or dead coin cell and main battery is being swapped.

AND one of the following conditions also applies:

1. The platform does not implement a power button to initiate a sequence to S0, and

AC power becomes available.

2. The platform does use a power button, but the default first sequence when power is

available is entry into S0.

In these cases, the relative timing between RTC and suspend wells becomes important.

The key point is that, as well as a minimum time, there is a maximum time by which

RTCRST_B must be deasserted. It must happen before an internal reset associated with

the suspend well is deasserted. This is shown in Figure 20.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

111

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