DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Clocking—Intel® Quark SoC X1000

Table 54.

Intel® Quark SoC X1000 Clock Inputs

Clock Domain

Main

Signal Name

XTAL_IN

XTAL_OUT

Frequency

25 MHz

RTC

RTCX1

RTCX2

32 kHz

Ethernet PHY

RMII_REF_CLK

50 MHz

Usage/Description

25 MHz reference for the iCLK PLL

RTC Crystal I/O for RTC block.

This clock is optional and may be

generated internally by the iCLK PLL.

RMII 50MHz Clock

This clock is a loopback of

RMII_REF_CLK_OUT

JTAG

TCK

25 MHz

JTAG Test Clock

Table 55.

Intel® Quark SoC X1000 Clock Outputs

Clock Domain

DDR

PCI Express*

Flex Clocks

Legacy SPI

SPI

Ethernet PHY

I2C*

SD

Main

Signal Name

DDR3_CK[1:0]

DDR3_CKB[3:0]

REF[0/1]_OUTCLK_N

REF[0/1]_OUTCLK_P

FLEX0_CLK

FLEX1_CLK

FLEX2_CLK

LSPI_SCK

SPI[0/1]_SCK

RMII_REF_CLK_OUT

I2C_CLK

SD_CLK

CKSYS25OUT

Frequency

400 MHz

100 MHz

33 MHz

33 MHz

48 MHz

20 MHz

25 MHz

50 MHz

400 kHz

50 MHz

25 MHz

§§

Usage/Description

Drives the Memory ranks 0-1. Data rate is

2x the clock rate.

Differential Clocks supplied to external PCI

Express* devices

Output clock for External devices

Clock for external SPI Flash

SPI serial clocks

Reference clock for RMII interface

I2C clocks

SD Clock

25 MHz Oscillator Output

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

101

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