DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Power Management—Intel® Quark SoC X1000

8.3.2.2

8.3.2.3

8.4

8.4.1

8.4.2

8.4.2.1

8.4.2.2

Core C1 State

C1 is a low power state entered when the core executes a HLT instruction.

A System Management Interrupt (SMI) handler returns execution to either Normal

state or the C1 state. See the Intel® 64 and IA-32 Architecture Software Developer’s

Manual, Volume 3A/3B: System Programmer’s Guide for more information.

While the core is in C1 state, it still processes snoops.

Core C2 State

C2 is entered when the processor reads the P_LVL2 register to trigger a transition from

C0 to C2. While the core is in the C2 state, it processes snoops.

An interrupt or a reset is required to exit the C2 state and return to the C0 state.

Memory Controller Power Management

The main memory is power managed during normal operation and in low-power ACPI

Cx states.

Disabling Unused System Memory Outputs

When a given rank is not populated, the corresponding chip select and CKE signals are

not driven.

At reset, all rows must be assumed to be populated, until it can be proven that they are

not populated. This is due to the fact that when CKE is tri-stated the memory module is

not guaranteed to maintain data integrity.

DRAM Power Management and Initialization

The SoC implements extensive support for power management on the SDRAM

interface. There are four SDRAM operations associated with the Clock Enable (CKE)

signals, SRE, SRX, PDE and PDX, which the SDRAM controller supports. The SoC drives

two CKE pins to perform these operations.

Initialization Role of CKE

During power-up, CKE is the only input to the SDRAM that is recognized (other than the

DDR3 reset pin) once power is applied. It must be driven LOW by the DDR controller to

make sure the SDRAM components float DQ and DQS during power-up.

CKE signals remain LOW (while any reset is active) until the BIOS writes to a

configuration register. Using this method, CKE is guaranteed to remain inactive for

much longer than the specified 200 micro-seconds after power and clocks to SDRAM

devices are stable.

Dynamic Self-Refresh

When Dynamic Self-Refresh (SR) is enabled, via DPMC0.DYNSREN, the Memory

Controller places the SDRAM in SR mode when the following conditions are true:

1. No requests are pending

2. Internal Request Status is low priority

3. No SR exit requests from the DDRIO (for RCOMP updates)

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

107

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