DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Power Up and Reset Sequence

9.2.2

Once in state S0 the SoC can be put to sleep, i.e., transitioned to sleep states S3 or S4/

S5, through appropriate settings of the Legacy Bridge ACPI registers PM1C.SLPTYPE

and PM1C.SLPEN.

A wake event is defined as a transition from state S3 to state S0. The chip can be

woken up via a number of mechanisms including specific register settings, or by

asserting specific SoC pins. A watchdog function in the Legacy Bridge can also trigger a

wake event.

In auto power button mode, if the SoC is placed in sleep state S4/S5, the system can

only be woken by the removal and reapplication of AC power. Since PWR_BTN is low it

will power up and transition directly back to S0 as described in the power up sequence.

There are two classes of reset associated with Intel® Quark SoC X1000:

• A cold reset means transitioning from S0 to S4/S5 and back to S0 again,

independent of the PWR_BTN value. This can only be initiated from state S0

through the register RSTC.COLD_RST. All registers except those driven by the RTC

supply are effectively reset.

• A warm reset resets CPU and peripheral blocks without the removal of the power

supplies. This can be initiated via a write to the register RSTC.WARM_RST or by

asserting the SoC pin, RESET_BTN (active low). It can occur only in state S0 and

after reset the SoC remains in state S0. RTC well and suspend well registers are left

unaffected.

A cold boot is the sequence where AC power is applied followed by an immediate

transition to S0 using the PWR_BTN signal or directly in auto power button mode.

Catastrophic shutdown can be carried out by holding PWR_BTN low for at least 3s.

This results in a direct return to the S4/S5 state. It can also be initiated by software

under specific error conditions.

The following sections provide more detail on these power-related functions.

RTC Power Well Transition: G5 to G3 State Transition

The transition to the G3 state is initiated when VCCRTC_3P3 is ramped. The sequence

is as follows:

1. VCCRTC_3P3 ramps. RTCRST_B should be low.

2. The SoC starts the real time clock oscillator.

3. A minimum of t1 units after VCCRTC_3P3 ramps external circuitry deasserts

RTCRST_B. The system is now in the G3 state.

Intel® Quark SoC X1000

DS

110

October 2013

Document Number: 329676-001US

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