DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Power Management—Intel® Quark SoC X1000

Table 57.

8.2.3

ACPI PM State Transition Rules (Sheet 2 of 2)

Present

State

Transition Trigger

Any Enabled Wake Event

G1/S3, G1/S4 Power button Override

Resume Well Power Failure

G2/S5

Any Enabled Wake Event

Power Failure or Removal

G3

Power Returns

Next State

G0/S0/C0

G2/S5

G3

G0/S0/C0

G3

Option to go to S0/C0 (reboot) or G2/S5 (stay

off until power button pressed or other enabled

wake event) or G1/S4 (if system state was S4

prior to the power failure). Some wake events

are preserved through a power failure.

Processor Idle States

Table 58.

8.2.4

Processor Core/ States Support

State

C0

C1

C2

Description

Active mode, processor executing code

AutoHALT state

Stop Grant state

Integrated Memory Controller States

Table 59.

8.2.5

Main Memory States

States

Powerup

Precharge Powerdown

Active Powerdown

Self-Refresh

PCIe* States

Description

CKE asserted. Active mode.

CKE de-asserted (not self-refresh) with all banks closed.

CKE de-asserted (not self-refresh) with at least one bank active.

CKE de-asserted using device self-refresh

Table 60.

PCIe* States

States

L0

L0s

L1

L3

Description

Full on – Active transfer state

First Active Power Management low power state – Low exit latency

Lowest Active Power Management - Longer exit latency

Lowest power state (power-off) – Longest exit latency

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

105

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