DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Mapping Address Spaces—Intel® Quark SoC X1000

6.1.1.1

Figure 13.

MMIO

The MMIO mappings are shown in Figure 13.

Physical Address Space - MMIO

4 Gbyte

Boot Vector

- 1 (FFFFFFFFh)

- 128 Kbyte (FFFE0000h)

MMIO

Local APIC

- 17 Mbyte (FEEFFFFFh)

- 18 Mbyte (FEE0 0000h)

HMBOUND

Low DRAM

PCI ECAM

HECREG + 256 Mbyte

HECREG

1 Mbyte

DOS DRAM

Physical Address

Space

By default, CPU core reads targeting the Boot Vector range (FFFFFFFFh-FFFE0000h)

are sent to the Legacy Bridge, and write accesses target DRAM. For secure SKU’s, reads

targeting the Boot Vector are decoded and routed to a Secure Root of Trust Boot ROM.

For non-secure SKU’s, reads targeting this region are routed to a boot SPI flash device

connected to the Legacy Bridge.

Upstream writes from the I/O fabric to the Local APIC range (FEE00000h-FEEFFFFFh)

are sent to the CPU core’s APIC.

Accesses in the 256 Mbyte PCI ECAM range starting at HECREG generate enhanced

PCI configuration register accesses when enabled (HECREG.EC_ENABLE). Unlike

traditional memory writes, writes to this range are non-posted when enabled. See

Chapter 5.0, “Register Access Methods” for more details.

All other downstream accesses in the MMIO range are decoded based on PCI resource

allocations. The subtractive agent (for unclaimed accesses) is the I/O Fabric. The I/O

Fabric returns an UNSUPPORTED REQUEST for unclaimed accesses.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

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