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DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH
Intel
Intel 
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Mapping Address Spaces
6.1.1.2
Figure 14.
DOS DRAM
The DOS DRAM is the memory space below 1 MByte. In general, accesses from a
processor targeting DOS DRAM target system DRAM. Exceptions are shown in
Figure 14.
Physical Address Space - DOS DRAM
4 Gbyte
MMIO
HMBOUND
Low DRAM
F Segment
E Segment
64 Kbyte (F0000h to F FFFFh)
64 Kbyte (E 0000h to E FFFFh)
VGA/CSEG
128 Kbyte (A0000h to BFFFFh)
6.1.1.3
1 Mbyte
DOS DRAM
Physical Address
Space
Processor writes to the 64 Kbyte (each) E and F segments (E0000h-EFFFFh and
F0000h-FFFFFh) always target DRAM. The HMISC2 register is used to direct CPU core
reads in these two segments to DRAM or the I/O fabric (MMIO).
CPU core accesses to the 128 Kbyte VGA/CSEG range (A0000h-BFFFFh) can target
DRAM or the MMIO space depending on the setting of HMISC2.ABSEG_IN_DRAM. When
targeting MMIO space, requests are sent to the PCIe* port if legacy VGA is enabled in
the PCIe controller.
Additional Mappings
There is one additional mapping available in the Host Bridge:
• SMM range
Figure 15 shows these mappings.
Intel® Quark SoC X1000
DS
92
October 2013
Document Number: 329676-001US

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