DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Mapping Address Spaces—Intel® Quark SoC X1000

Figure 15. Physical Address Space - SMM Range

L o w o r H ig h

D R A M in P h y s ic a l

Space

SM M Range

H S M M C T L.S M M _ E N D

H S M M C T L.S M M _ S T A R T

6.1.2

Table 50.

Warning:

6.2

0

SMI handlers running on a CPU core execute out of SMRAM. To protect this memory

from non-CPU core access, the SMM Range (HSMMCTL.SMM_START -

HSMMCTL.SMM_END) may be programmed anywhere in low DRAM space (1 Mbyte

aligned). This range only allows accesses from the CPU core while in SMM.

MMIO Map

Memory accesses targeting MMIO are routed by the programmed PCI ranges.

Fixed MMIO is claimed by the Legacy Bridge. The default regions are listed below.

Movable ranges are not shown. See the register maps of all Legacy Bridge components

for details.

Fixed Memory Ranges in the Legacy Bridge

Device

Low BIOS (Flash Boot)

I/O APIC

HPET

High BIOS/Boot Vector

Start Address End Address

Comments

000E0000h

FEC00000h

FED00000h

FFFE0000h

000FFFFFh

FEC00040h

FED003FFh

FFFFFFFFh

Starts 128 Kbyte below 1 Mbyte; Firmware/

BIOS

Starts 20 Mbyte below 4 Gbyte

Starts 19 Mbyte below 4 Gbyte

Starts 128 Kbyte below 4 Gbyte; Firmware/

BIOS

PCI devices may also claim memory resources in MMIO space. For details see each

device’s interface chapter.

Variable memory ranges should not be set to conflict with other memory ranges. There

may be unpredictable results if the configuration software allows conflicts to occur.

Hardware does not check for conflicts.

I/O Address Space

There are 64 Kbyte + 3 bytes of I/O space (0h-10002h) for accessing I/O registers.

Most I/O registers exists for legacy functions in the Legacy Bridge or for PCI devices,

while some are claimed by the Host Bridge for the PCI configuration space access

registers.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

93

Share Link: