DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Mapping Address Spaces

6.2.1

6.2.2

6.2.2.1

Table 51.

6.2.2.2

Warning:

Table 52.

Host Bridge I/O Map

The Host Bridge claims I/O transactions for VGA/Extended VGA found in the display/

graphics interface. It also claims the two 32-bit registers at port CF8h and CFCh used

to access PCI configuration space.

I/O Fabric I/O Map

Legacy Bridge Fixed I/O Address Ranges

Table 51 shows the fixed I/O space ranges seen by a processor.

Fixed I/O Ranges in the Legacy Bridge

Device

8259 Master

8254s

NMI Controller

RTC

Scratch Pad

8259 Slave

Reset Control

I/O Address

20h-3Dh

40h-43h, 50h-53h

61h, 63h, 65h, 67h

70h-73h

80h-83h

A0h-BDh

CF9h

Comments

Overlaps PCI I/O registers

Variable I/O Address Ranges

Table 52 shows the variable I/O decode ranges. They are set using base address

registers (BARs) or other similar means. Plug-and-play (PnP) software (PCI/ACPI) can

use their configuration mechanisms to set and adjust these values.

The variable I/O ranges should not be set to conflict with other I/O ranges. There may

be unpredictable results if the configuration software allows conflicts to occur.

Hardware does not check for conflicts.

Movable I/O Ranges Decoded by PCI Devices on the I/O Fabric

Device

ACPI Power Management

ACPI General Purpose Event 0

GPIO

Watchdog Timer

ACPI Processor Block

SPI DMA Block

Size (bytes)

16

64

128

64

16

16

Target

PM1BLK: PCI[B:0,D:31,F:0] + 48h

GPE0BLK: PCI[B:0,D:31,F:0] + 4Ch

GBA: PCI[B:0,D:31,F:0] + 44h

WDTBA: PCI[B:0,D:31,F:0] + 84h

PMBA: Port[0x04] + 70h

SPI_DMA_BAR: Port[0x04] + 7Ah

Intel® Quark SoC X1000

DS

94

October 2013

Document Number: 329676-001US

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