DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Power Up and Reset Sequence—Intel® Quark SoC X1000
9.0
9.1
9.1.1
9.2
9.2.1
Power Up and Reset Sequence
This chapter provides information on the following topics:
• Power up and down sequences, including wake events
• Reset behavior
Intel® Quark SoC X1000 System States
System Sleeping States Control (S-States)
The SoC supports the S0, S3, S4, and S5 sleep states. S4 and S5 states are identical
from a hardware perspective.
The SoC integrates a Power Management Controller (PMC). No external power
controller IC is required.
The SoC sleep states are described in Chapter 8.0, “Power Managementâ€.
Power Up and Down Sequences
Power Up, Wake and Reset Overview
SoC power up is dependent on two supplies:
• VCC3P3_S5, which is generated from AC power
• VCCRTC_3P3, which powers the RTC well only
VCCRTC_3P3 is derived directly from VCC3P3_S5, if present. Otherwise it can be driven
by a coin-cell battery.
• In the case where the coin-cell battery is present but not AC power, only the RTC
well is powered up. The SoC can move to state G3 only. The SoC can subsequently
be transitioned to state S4/S5 by applying AC power.
• In the case where AC power is present but there is no coin-cell battery, power up is
initiated directly by the ramping of the VCC3P3_S5 supply. The SoC transitions
directly to state S4/S5.
Subsequent transition from S4/S5 to S0 is governed by activity on the power button
pin, PWR_BTN:
• If PWR_BTN is strapped low (auto power button mode) when AC power is applied,
the SoC transitions directly to S0 from S4/S5 via a transitional S3 state.
• If PWR_BTN is high when AC power is applied, the SoC transitions to S4/S5 only. A
subsequent falling edge on PWR_BTN, with the low value being maintained for
2.5ms or more, is required to initiate a transition to S0 via the transitional S3 state.
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
109
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