DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Power Management

Note:

8.2.1.4

8.2.2

This is a software based state that is the same as S5 to hardware. On S4 entry, the

system saves the entire contents of data off to NVRAM. On S4 resume, the system

restores the entire contents of memory after performing the a typical S5-S0 boot.

Key features:

• No activity is allowed.

• All power wells are disabled, except for the suspend and RTC well.

S5 - Soft Off

From a hardware perspective the S5 state is identical to the S4 state. The difference is

purely software; software does not write system context to OS storage when entering

S5.

System States

Table 56.

Table 57.

General Power States for System

States/Sub-states

Legacy Name / Description

G0/S0/C0

G0/S0/Cx

G1/S3

G1/S4

G2/S5

G3

FULL ON: CPU operating. Individual devices may be shut down to save power. The

different CPU operating levels are defined by Cx states.

Cx State: CPU manages C-state itself.

Suspend-To-RAM (STR): The system context is maintained in system DRAM, but

power is shut to non-critical circuits. Memory is retained, and refreshes continue. All

external clocks are shut off; RTC clock and internal ring oscillator clocks are still

toggling.

Suspend-To-Disk (STD): The context of the system is maintained on the disk. All

power is shut down except power for the logic to resume.

Soft-Off: System context is not maintained. All power is shut down except power for

the logic to restart. A full boot is required to restart. A full boot is required when

waking.

Mechanical OFF. System content is not maintained. All power shutdown except for

the RTC. No “Wake” events are possible, because the system does not have any

power. This state occurs if the user removes the batteries, turns off a mechanical

switch, or if the system power supply is at a level that is insufficient to power the

“waking” logic. When system power returns, transition depends on the state just prior

to the entry to G3.

Table 57 shows the transition rules among the various states. Note that transitions

among the various states may appear to temporarily transition through intermediate

states. These intermediate transitions and states are not listed in the table.

ACPI PM State Transition Rules (Sheet 1 of 2)

Present

State

G0/S0/C0

G0/S0/C2

Transition Trigger

Next State

P_LVL2 Read

PM1C.SLP_EN bit set

Power Button Override

Mechanical Off/Power Failure

C2 break events which include: MSI, Legacy

Interrupt

Power Button Override

Resume Well Power Failure

G0/S0/C2

G1/Sx or G2/S5 state (specified by

PM1C.SLP_TYPE)

G2/S5

G3

G0/S0/C0

G2/S5

G3

Intel® Quark SoC X1000

DS

104

October 2013

Document Number: 329676-001US

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