DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Power Management
8.2.6
Interface State Combinations
Table 61.
G, S and C State Combinations
Global (G)
State
G0
G0
G0
Sleep
(S) State
S0
S0
S0
Processor
Core
(C) State
C0
C1
C2
G1
S3
Power Off
G1
S4
Power Off
G2
S5
Power Off
G3
NA
Power Off
Processor State
System
Clocks
Full On
Auto-Halt
Stop Grant
On
On
On
Off except RTC
& internal ring
OSC
Off except RTC
& internal ring
OSC
Off except RTC
& internal ring
OSC
Power Off
Description
Full On
Auto-Halt
Stop Grant
Suspend to RAM
Suspend to Disk
Soft Off
Hard Off
8.3
8.3.1
8.3.1.1
8.3.2
8.3.2.1
Processor Core Power Management
When the processor is not executing code, it is idle. A low-power idle state is defined by
ACPI as a C-state. In general, lower power C-states have longer entry and exit
latencies.
Low-Power Idle States
When the processor core is idle, low-power idle states (C-states) are used to save
power. More power savings actions are taken for numerically higher C-state. However,
higher C-states have longer exit and entry latencies.
Clock Control and Low-Power States
The processor core supports low power states at core level. States for processor core
include Normal (C0), Auto-Halt (C1) and Stop Grant (C2).
Transition to processor core power states higher than C1 are triggered by initiating a
P_LVLx (P_LVL2) I/O read.
The Cx state ends due to a break event. Based on the break event, the processor
returns the system to C0. The following are examples of such break events:
• Any unmasked interrupt goes active
• Any internal event that will cause an NMI or SMI_B
• CPU Pending Break Event (PBE_B)
• MSI
Processor Core C-States Description
Core C0 State
The normal operating state of a core where code is being executed.
Intel® Quark SoC X1000
DS
106
October 2013
Document Number: 329676-001US
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