DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Power Management

8.4.2.3

8.4.2.4

If one of the above conditions change prior to the SR Entry command being sent to the

DRAM the process is terminated.

When Dynamic SR is enabled the Memory Controller exits SR mode when one of the

following is true:

1. Requests are pending and the Internal Request Status is normal or urgent

2. A SR exit request from the DDRIO

Dynamic Power Down Operation

Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The Memory Controller

implements aggressive CKE control to dynamically put the DRAM devices in a power

down state. The Memory Controller can be configured to put the devices in active

power down (CKE de-assertion with open pages) or precharge power down (CKE de-

assertion with all pages closed). Precharge power down provides greater power savings

but has a bigger performance impact, since all pages will first be closed before putting

the devices in power down mode.

If dynamic power-down is enabled, all ranks are powered up before doing a refresh

cycle and all ranks are powered down at the end of refresh.

Functional Clock Gating

The Memory Controller has internal clock gating for the majority of its clocked logic.

When enabled the clock gating is activated when all inputs are inactive and all

commands are complete and DDR3 timing trackers are flushed. When Dynamic SR is

enabled, clock gating is only applied when the SDRAM is in Self-Refresh.

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Intel® Quark SoC X1000

DS

108

October 2013

Document Number: 329676-001US

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