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AT90PWM2(2005) View Datasheet(PDF) - Atmel Corporation

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AT90PWM2 Datasheet PDF : 365 Pages
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AT90PWM2/3
EEWE has been set, the CPU is halted for two cycles before the next instruction is
executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction, and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation
is in progress, it is neither possible to read the EEPROM, nor to change the EEAR
Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical
programming time for EEPROM access from the CPU.
Table 2. EEPROM Programming Time.
Symbol
Number of Calibrated RC Oscillator Cycles Typ Programming Time
EEPROM write
(from CPU)
67 584
8.5 ms
Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.
25
4317B–AVR–02/05

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