Watchdog Reset
When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT-
in Figure 21), the Brown-out Reset is immediately activated. When VCC increases above
the trigger level (VBOT+ in Figure 21), the delay counter starts the MCU after the Time-
out period tTOUT has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level
for longer than tBOD given in Table 16.
Figure 21. Brown-out Reset During Operation
VCC
VBOT-
VBOT+
RESET
TIME-OUT
tTOUT
INTERNAL
RESET
When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
tTOUT. Refer to page 50 for details on operation of the Watchdog Timer.
Figure 22. Watchdog Reset During Operation
CC
CK
MCU Status Register –
MCUSR
The MCU Status Register provides information on which reset source caused an MCU
reset.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
WDRF BORF EXTRF PORF MCUSR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
See Bit Description
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
48 AT90PWM2/3
4317B–AVR–02/05