AT90PWM2(2005) View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT90PWM2
(Rev.:2005)

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

4317B–AVR–02/05

AT90PWM2/3

Table 20. Reset and Interrupt Vectors

Vector

No.

Program

Address

Source

30

0x001D

31

0x001E

32

0x001F SPM READY

Interrupt Definition

Store Program Memory Ready

Notes:

1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader

address at reset, see “Boot Loader Support – Read-While-Write Self-Programming”

on page 273.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of

the Boot Flash Section. The address of each Interrupt Vector will then be the address

in this table added to the start address of the Boot Flash Section.

Table 21 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these loca-

tions. This is also the case if the Reset Vector is in the Application section while the

Interrupt Vectors are in the Boot section or vice versa.

Table 21. Reset and Interrupt Vectors Placement in AT90PWM2/3(1)

BOOTRST IVSEL Reset Address

Interrupt Vectors Start Address

1

0

0x000

0x001

1

1

0x000

Boot Reset Address + 0x001

0

0

Boot Reset Address

0x001

0

1

Boot Reset Address

Boot Reset Address + 0x001

Note: 1. The Boot Reset Address is shown in Table 114 on page 286. For the BOOTRST

Fuse “1” means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector

Addresses in AT90PWM2/3 is:

Address Labels Code

Comments

0x000

0x001

rjmp RESET

rjmp PSC2_CAPT

; Reset Handler

; PSC2 Capture event Handler

0x002

rjmp PSC2_EC

; PSC2 End Cycle Handler

0x003

rjmp PSC1_CAPT

; PSC1 Capture event Handler

0x004

rjmp PSC1_EC

; PSC1 End Cycle Handler

0x005

rjmp PSC0_CAPT

; PSC0 Capture event Handler

0x006

0x007

rjmp PSC0_EC

rjmp ANA_COMP_0

; PSC0 End Cycle Handler

; Analog Comparator 0 Handler

0x008

rjmp ANA_COMP_1

; Analog Comparator 1 Handler

0x009

0x00A

rjmp ANA_COMP_2

rjmp EXT_INT0

; Analog Comparator 2 Handler

; IRQ0 Handler

0x00B

rjmp TIM1_CAPT

; Timer1 Capture Handler

0x00C

rjmp TIM1_COMPA

; Timer1 Compare A Handler

0x00D

rjmp TIM1_COMPB

; Timer1 Compare B Handler

57

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