0x00F
rjmp TIM1_OVF
; Timer1 Overflow Handler
0x010
rjmp TIM0_COMPA
; Timer0 Compare A Handler
0x011
rjmp TIM0_OVF
; Timer0 Overflow Handler
0x012
Handler
rjmp ADC
; ADC Conversion Complete
0x013
rjmp EXT_INT1
; IRQ1 Handler
0x014
rjmp SPI_STC
; SPI Transfer Complete Handler
0x015
rjmp USART_RXC
; USART, RX Complete Handler
0x016
rjmp USART_UDRE
; USART, UDR Empty Handler
0x017
rjmp USART_TXC
; USART, TX Complete Handler
0x018
0x019
0x01A
rjmp
rjmp
rjmp
EXT_INT2
WDT
EE_RDY
; IRQ2 Handler
; Watchdog Timer Handler
; EEPROM Ready Handler
0x01B
rjmp TIM0_COMPB
; Timer0 Compare B Handler
0x01C
rjmp EXT_INT3
; IRQ3 Handler
0x01F
Handler
;
0x020RESET:
rjmp SPM_RDY
; Store Program Memory Ready
ldi r16, high(RAMEND); Main program start
0x021
RAM
out SPH,r16
; Set Stack Pointer to top of
0x022
ldi r16, low(RAMEND)
0x023
0x024
out SPL,r16
sei
; Enable interrupts
0x025
<instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and
the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most
typical and general program setup for the Reset and Interrupt Vector Addresses in
AT90PWM2/3 is:
Address Labels Code
Comments
0x000 RESET: ldi r16,high(RAMEND); Main program start
0x001
RAM
0x002
out SPH,r16
; Set Stack Pointer to top of
ldi r16,low(RAMEND)
0x003
0x004
out SPL,r16
sei
; Enable interrupts
0x005
<instr> xxx
;
.org 0xC01
0xC01
rjmp PSC2_CAPT
; PSC2 Capture event Handler
0xC02
rjmp PSC2_EC
; PSC2 End Cycle Handler
...
0xC1F
Handler
... ...
rjmp SPM_RDY
;
; Store Program Memory Ready
58 AT90PWM2/3
4317B–AVR–02/05