AT90PWM2/3/2B/3B
Figure 20-1. Analog Comparator Block Diagram(1)(2)
ACMP0
CLK I/O (/2)
+
-
AC0EN
Interrupt Sensitivity Control
AC0IS1 AC0IS0
AC0O
AC0IF
Analog Comparator 0 Interrupt
AC0IE
ACMP1
ACMP2
ACMPM
DAC
Vref
DAC
Result
Aref
AVcc
Internal 2.56V
Reference
DACEN
REFS0
REFS1
/1.60
/2.13
/3.20
/6.40
AC0M
210
CLK I/O (/2)
+
-
AC1EN
Interrupt Sensitivity Control
AC1IS1 AC1IS0
AC1M
210
CLK I/O (/2)
+
-
AC2EN
Interrupt Sensitivity Control
AC2IS1 AC2IS0
AC1O
AC1IF
Analog Comparator 1 Interrupt
AC1IE
T1 Capture Trigger
AC1ICE
AC2O
AC2IF
Analog Comparator 2 Interrupt
AC0IE
AC2M
210
Notes: 1. ADC multiplexer output: see Table 21-4 on page 248.
2. Refer to Figure 3-1 on page 3 and for Analog Comparator pin placement.
3. The voltage on Vref is defined in 21-3 “ADC Voltage Reference Selection” on page 247
20.2
Analog Comparator Register Description
Each analog comparator has its own control register.
A dedicated register has been designed to consign the outputs and the flags of the 3 analog
comparators.
20.2.1
Analog Comparator 0 Control Register – AC0CON
Bit
Read/Write
Initial Value
7
6
5
4
3
2
AC0EN
AC0IE
AC0IS1
AC0IS0
-
AC0M2
R/W
R/W
R/W
R/W
-
R/W
0
0
0
0
0
0
• Bit 7– AC0EN: Analog Comparator 0 Enable Bit
Set this bit to enable the analog comparator 0.
Clear this bit to disable the analog comparator 0.
• Bit 6– AC0IE: Analog Comparator 0 Interrupt Enable bit
Set this bit to enable the analog comparator 0 interrupt.
Clear this bit to disable the analog comparator 0 interrupt.
1
AC0M1
R/W
0
0
AC0M0
R/W
0
AC0CON
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