AT90PWM2/3/2B/3B
7.1.5
ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
7.2 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as illustrated
Table 7-1. The clock from the selected source is input to the AVR clock generator, and routed to
the appropriate modules.
Table 7-1. Device Clocking Options Select(1) AT90PWM2/3
Device Clocking Option
External Crystal/Ceramic Resonator
Reserved
PLL output divided by 4 : 16 MHz
Calibrated Internal RC Oscillator
Reserved
External Clock
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
CKSEL3..0
1111 - 1000
0111- 0100
0011
0010
0001
0000
Table 7-2. Device Clocking Options Select AT90PWM2B/3B
Device Clocking Option
External Crystal/Ceramic Resonator
System
Clock
Ext Osc (2)
PLL Input
RC Osc (3)
PLL output divided by 4 : 16 MHz / External
Crystal/Ceramic Resonator/ PLL driven by External Crystal
/Ceramic Resonator
Ext Osc
Ext Osc
PLL output divided by 4 : 16 MHz / PLL driven by External
Crystal/Ceramic Resonator
PLL / 4
Ext Osc
Reserved
N/A
N/A
PLL output divided by 4 : 16 MHz
PLL / 4
RC Osc
Calibrated Internal RC Oscillator
RC Osc RC Osc
PLL output divided by 4 : 16 MHz / PLL driven by External
clock
PLL / 4
Ext Clk (4)
External Clock
Ext Clk
RC Osc
1.For all fuses “1” means unprogrammed while “0” means programmed
2.Ext Osc : External Osc
3.RC Osc : Internal RC Oscillator
4.Ext Clk : External Clock Input
CKSEL3..0
(1)
1111 - 1000
0100
0101
0111- 0110
0011
0010
0001
0000
4317K–AVR–03/2013
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
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