AT90PWM2B-16SU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT90PWM2B-16SU

8-bit Atmel Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

Figure 7-6. External Clock Drive Configuration

NC

External

Clock

Signal

AT90PWM2/3/2B/3B

XTAL2

XTAL1

GND

Table 7-10.

CKSEL3..0

0000

External Clock Frequency

Frequency Range

0 - 16 MHz

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 7-11.

Table 7-11. Start-up Times for the External Clock Selection

SUT1..0

00

Start-up Time from Power-

down and Power-save

6 CK

Additional Delay from

Reset (VCC = 5.0V)

14CK

Recommended Usage

BOD enabled

01

6 CK

14CK + 4.1 ms

Fast rising power

10

6 CK

14CK + 65 ms

Slowly rising power

11

Reserved

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

38 for details.

7.9 Clock Output Buffer

When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is

suitable when chip clock is used to drive other circuits on the system. The clock will be output

also during reset and the normal operation of I/O pin will be overridden when the fuse is pro-

grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO

serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that

is output (CKOUT Fuse programmed).

7.10 System Clock Prescaler

The AT90PWM2/2B/3/3B system clock can be divided by setting the Clock Prescale Register –

CLKPR. This feature can be used to decrease power consumption when the requirement for

processing power is low. This can be used with all clock source options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH

are divided by a factor as shown in Table 7-12.

38

4317K–AVR–03/2013

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