DSPIC33FJ64GP706AI/PF View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ64GP706AI/PF Datasheet PDF : 350 Pages
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dsPIC33FJXXXGPX06A/X08A/X10A
REGISTER 20-1: DCICON1: DCI CONTROL REGISTER 1
R/W-0
DCIEN
bit 15
U-0
R/W-0
U-0
R/W-0
—
DCISIDL
—
DLOOP
R/W-0
CSCKD
R/W-0
CSCKE
R/W-0
COFSD
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
UNFM
CSDOM
DJST
—
—
bit 7
U-0
R/W-0
R/W-0
—
COFSM<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4-2
bit 1-0
DCIEN: DCI Module Enable bit
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
DCISIDL: DCI Stop in Idle Control bit
1 = Module will halt in CPU Idle mode
0 = Module will continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
DLOOP: Digital Loopback Mode Control bit
1 = Digital Loopback mode is enabled. CSDI and CSDO pins internally connected
0 = Digital Loopback mode is disabled
CSCKD: Sample Clock Direction Control bit
1 = CSCK pin is an input when DCI module is enabled
0 = CSCK pin is an output when DCI module is enabled
CSCKE: Sample Clock Edge Control bit
1 = Data changes on serial clock falling edge, sampled on serial clock rising edge
0 = Data changes on serial clock rising edge, sampled on serial clock falling edge
COFSD: Frame Synchronization Direction Control bit
1 = COFS pin is an input when DCI module is enabled
0 = COFS pin is an output when DCI module is enabled
UNFM: Underflow Mode bit
1 = Transmit last value written to the transmit registers on a transmit underflow
0 = Transmit ‘0’s on a transmit underflow
CSDOM: Serial Data Output Mode bit
1 = CSDO pin will be tri-stated during disabled transmit time slots
0 = CSDO pin drives ‘0’s during disabled transmit time slots
DJST: DCI Data Justification Control bit
1 = Data transmission/reception is begun during the same serial clock cycle as the frame
synchronization pulse
0 = Data transmission/reception is begun one serial clock cycle after frame synchronization pulse
Unimplemented: Read as ‘0’
COFSM<1:0>: Frame Sync Mode bits
11 = 20-bit AC-Link mode
10 = 16-bit AC-Link mode
01 = I2S Frame Sync mode
00 = Multi-Channel Frame Sync mode
© 2011 Microchip Technology Inc.
DS70593C-page 233
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