DSPIC33FJ32MC304-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ32MC304-I/SP

16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Motor Control PWM and Advanced Analog

Microchip Technology 

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04

20.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC302/304,

dsPIC33FJ64MCX02/X04

and

dsPIC33FJ128MCX02/X04 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 17. “UART”

(DS70188) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules

available in the dsPIC33FJ32MC302/304,

dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/

X04 device family. The UART is a full-duplex

asynchronous system that can communicate with

peripheral devices, such as personal computers,

LIN 2.0, RS-232 and RS-485 interfaces. The module

also supports a hardware flow control option with the

UxCTS and UxRTS pins and also includes an IrDA®

encoder and decoder.

The primary features of the UART module are:

• Full-Duplex, 8- or 9-bit Data Transmission through

the UxTX and UxRX pins

• Even, Odd or No Parity options (for 8-bit data)

• One or two stop bits

• Hardware flow control option with UxCTS and

UxRTS pins

• Fully integrated Baud Rate Generator with 16-bit

prescaler

• Baud rates ranging from 10 Mbps to 38 bps at

40 MIPS

• Baud rates ranging from 4 Mbps to 61 bps at 4x mode

at 40 MIPS

• 4-deep First-In First-Out (FIFO) Transmit Data

buffer

• 4-deep FIFO Receive Data buffer

• Parity, framing and buffer overrun error detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive interrupts

• A separate interrupt for all UART error conditions

• Loopback mode for diagnostic support

• Support for sync and break characters

• Support for automatic baud rate detection

• IrDA® encoder and decoder logic

• 16x baud clock output for IrDA® support

A simplified block diagram of the UART module is

shown in Figure 20-1. The UART module consists of

these key hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 20-1:

UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA®

Hardware Flow Control

UART Receiver

UxRTS/BLCKx

UxCTS

UxRX

UART Transmitter

UxTX

Note 1: Both UART1 and UART2 can trigger a DMA data transfer.

2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word

(i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00).

© 2007-2012 Microchip Technology Inc.

DS70291G-page 247

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