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DSPIC33FJ32MC304-I/SP View Datasheet(PDF) - Microchip Technology

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Description
Manufacturer
DSPIC33FJ32MC304-I/SP Datasheet PDF : 460 Pages
First Prev 241 242 243 244 245 246 247 248 249 250 Next Last
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
bit 3
bit 2-1
bit 0
URXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0
0 = UxRX Idle state is ‘1
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
DS70291G-page 250
© 2007-2012 Microchip Technology Inc.

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