DSPIC33FJ32MC304-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ32MC304-I/SP

16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Motor Control PWM and Advanced Analog

Microchip Technology 

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04

26.0 PROGRAMMABLE CYCLIC

REDUNDANCY CHECK (CRC)

GENERATOR

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC302/304,

dsPIC33FJ64MCX02/X04

and

dsPIC33FJ128MCX02/X04 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 36.

“Programmable Cyclic Redundancy

Check (CRC)” (DS70298) of the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip

web

site

(www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The programmable CRC generator offers the following

features:

• User-programmable polynomial CRC equation

• Interrupt output

• Data FIFO

FIGURE 26-1:

CRC SHIFTER DETAILS

26.1 Overview

The module implements a software configurable CRC

generator. The terms of the polynomial and its length

can be programmed using the CRCXOR bits (X<15:1>)

and the CRCCON bits (PLEN<3:0>), respectively.

EQUATION 26-1: CRC EQUATION

16 12 5

x +x +x +1

To program this polynomial into the CRC generator,

the CRC register bits should be set as shown in

Table 26-1.

TABLE 26-1: EXAMPLE CRC SETUP

Bit Name

Bit Value

PLEN<3:0>

X<15:1>

1111

000100000010000

For the value of X<15:1>, the 12th bit and the 5th bit are

set to ‘1’, as required by the CRC equation. The 0th bit

required by the CRC equation is always XORed. For a

16-bit polynomial, the 16th bit is also always assumed

to be XORed; therefore, the X<15:1> bits do not have

the 0th bit or the 16th bit.

The topology of a standard CRC generator is shown in

Figure 26-2.

PLEN<3:0>

0

Hold

XOR

DOUT

OUT

IN

BIT 0

p_clk

1

2

X1

Hold

CRC Shift Register

X2

Hold

0

OUT

IN

BIT 1

1

p_clk

0

OUT

IN

BIT 2

1

p_clk

15

X3 X15

Hold

0

0

OUT

IN

1

1

BIT 15

p_clk

CRC Read Bus

CRC Write Bus

© 2007-2012 Microchip Technology Inc.

DS70291G-page 321

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