dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
27.2 PMP Control Registers
REGISTER 27-1: PMCON: PARALLEL PORT CONTROL REGISTER
R/W-0
U-0
PMPEN
—
bit 15
R/W-0
PSIDL
R/W-0
R/W-0
ADRMUX1(1) ADRMUX0(1)
R/W-0
PTBEEN
R/W-0
PTWREN
R/W-0
PTRDEN
bit 8
R/W-0
CSF1
bit 7
R/W-0
CSF0
R/W-0
ALP(2)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CS1P(2)
BEP
WRSP
RDSP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-6
bit 5
bit 4
bit 3
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1)
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on
PMA<10:8>
00 = Address and data appear on separate pins
PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
CSF1:CSF0: Chip Select Function bits
11 = Reserved
10 = PMCS1 functions as chip select
0x = PMCS1 functions as address bit 14
ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Unimplemented: Read as ‘0’
CS1P: Chip Select 1 Polarity bit(2)
1 = Active-high (PMCS1/PMCS1)
0 = Active-low (PMCS1/PMCS1)
Note 1: 28-pin devices do not have PMA<10:2>.
2: These bits have no effect when their corresponding pins are used as address lines.
© 2007-2012 Microchip Technology Inc.
DS70291G-page 329