STM32F373VBT7(2013) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32F373VBT7
(Rev.:2013)
(Rev.:2013)
STMicroelectronics
STM32F373VBT7 Datasheet PDF : 131 Pages
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STM32F37xxx
Electrical characteristics
6.3.21
6.3.22
VBAT monitoring characteristics
Symbol
Table 67. VBAT monitoring characteristics
Parameter
Min Typ
R
Q
Er(1)
TS_vbat(2)
Resistor bridge for VBAT
Ratio on VBAT measurement
Error on Q
ADC sampling time when reading the VBAT
1mV accuracy
-
50
-
2
-1
-
5
-
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
Max
-
-
+1
-
Unit
KΩ
%
µs
Timer characteristics
The parameters given in Table 68 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 68. TIMx(1) (2)characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tres(TIM)
fEXT
ResTIM
Timer resolution time
fTIMxCLK = 72 MHz
Timer external clock
frequency on CH1 to CH4 fTIMxCLK = 72 MHz
Timer resolution
TIMx (except
TIM2)
TIM2
1
13.9
0
0
-
-
-
-
fTIMxCLK/2
24
16
32
tTIMxCLK
ns
MHz
MHz
bit
tCOUNTER 16-bit counter clock period
tMAX_COUN Maximum possible count
T
with 32-bit counter
fTIMxCLK = 72 MHz
fTIMxCLK = 72 MHz
1
0.0139
-
-
65536
910
65536 × 65536
59.65
tTIMxCLK
µs
tTIMxCLK
s
1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14,
TIM15, TIM16 , TIM17, TIM18 and TIM19 timers.
2. Data based on characterization results, not tested in production.
Table 69. IWDG min/max timeout period at 40 kHz (LSI) (1)(2)
Prescaler divider PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4
0
0.1
/8
1
0.2
/16
2
0.4
409.6
819.2
1638.4
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