Table 68. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tS(1)
Sampling time
TADCVREG_STUP(1) ADC Voltage Regulator Start-up time
tCONV(1)
Total conversion time (including
sampling time)
CMIR(1)
Common Mode Input signal Range
fADC = 72 MHz
-
-
fADC = 72 MHz
Resolution = 12 bits
Resolution = 12 bits
ADC differential mode
0.021
-
8.35
1.5
-
601.5
-
-
10
0.19
-
8.52
14 to 614 (tS for sampling + 12.5 for successive
approximation)
(VSSA+VREF+)/2
-10%
(VSSA+VREF+)/2
(VSSA+VREF+)/2
+ 10%
µs
1/fADC
µs
µs
1/fADC
V
1. Data guaranteed by design.
2.
VfuRrtEhFe+r
can be internally
details.
connected
to
VDDA
and
VREF-
can
be
internally
connected
to
VSSA,
depending
on
the
package.
Refer
to
Section
4:
Pinouts
and
pin
description
for