DSPIC33FJ06GS502-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ06GS502-I/ML

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

U-0

U-0

R/W-0

U-0

U-0

U-0

U-0

—

—

INT2IE

—

—

—

—

bit 15

U-0

—

bit 8

U-0

—

bit 7

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

—

—

INT1IE

CNIE

AC1IE(1)

MI2C1IE

SI2C1IE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-14

bit 13

bit 12-5

bit 4

bit 3

bit 2

bit 1

bit 0

Unimplemented: Read as ‘0’

INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

Unimplemented: Read as ‘0’

INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

AC1IE: Analog Comparator 1 Interrupt Enable bit(1)

1 = Interrupt request enabled

0 = Interrupt request not enabled

MI2C1IE: I2C1 Master Events Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

SI2C1IE: I2C1 Slave Events Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

Note 1: This bit is not implemented in dsPIC33FJ06GS101/102 and dsPIC33FJ16GS402/404 devices.

© 2009 Microchip Technology Inc.

Preliminary

DS70318D-page 113

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