DSPIC33FJ16GS204-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ16GS204-I/SP

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

13.0 INPUT CAPTURE

Note:

This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “dsPIC33F Family

Reference Manual”, Section 12. “Input

Capture” (DS70198), which is available

on the Microchip web site

(www.microchip.com).

The input capture module is useful in applications

requiring frequency (period) and pulse measurement.

The

dsPIC33FJ06GS101/X02

and

dsPIC33FJ16GSX02/X04 devices support up to two

input capture channels.

The input capture module captures the 16-bit value of

the selected Time Base register when an event occurs

at the ICx pin. The events that cause a capture event

are listed below in three categories:

• Simple Capture Event modes:

- Capture timer value on every falling edge of

input at ICx pin

- Capture timer value on every rising edge of

input at ICx pin

• Capture timer value on every edge (rising and

falling)

• Prescaler Capture Event modes:

- Capture timer value on every 4th rising edge

of input at ICx pin

- Capture timer value on every 16th rising

edge of input at ICx pin

Each input capture channel can select one of the

two 16-bit timers (Timer2 or Timer3) for the time

base. The selected timer can use either an internal

or external clock.

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on input capture event

• 4-word FIFO buffer for capture values

- Interrupt optionally generated after 1, 2, 3 or

4 buffer locations are filled

• Use of input capture to provide additional sources

of external interrupts

FIGURE 13-1:

INPUT CAPTURE BLOCK DIAGRAM

From 16-Bit Timers

TMR2 TMR3

ICx Pin

Prescaler

Counter

(1, 4, 16)

Edge Detection Logic

and

Clock Synchronizer

ICM<2:0> (ICxCON<2:0>)

3

Mode Select

ICOV, ICBNE (ICxCON<4:3>)

ICxI<1:0>

ICxCON

FIFO

R/W

Logic

Interrupt

Logic

16 16

ICTMR

1

0 (ICxCON<7>)

ICxBUF

System Bus

Set Flag ICxIF

(in IFSx Register)

Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

© 2009 Microchip Technology Inc.

Preliminary

DS70318D-page 191

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