DSPIC33FJ16GS204-I/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ16GS204-I/SP Datasheet PDF : 346 Pages
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
14.1 Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 14-1 lists the different bit settings for the Output
Compare modes. Figure 14-2 illustrates the output
compare operation for various modes. The user
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
Note:
Refer to Section 13. “Output Compare”
in the “dsPIC33F Family Reference Man-
ual” (DS7029) for OCxR and OCxRS reg-
ister restrictions.
TABLE 14-1: OUTPUT COMPARE MODES
OCM<2:0>
Mode
OCx Pin Initial State
OCx Interrupt Generation
000 Module Disabled
Controlled by GPIO register
—
001 Active-Low One-Shot
0
OCx rising edge
010 Active-High One-Shot
1
OCx falling edge
011 Toggle
Current output is maintained OCx rising and falling edge
100 Delayed One-Shot
0
OCx falling edge
101 Continuous Pulse
0
OCx falling edge
110 PWM without Fault Protection
‘0’, if OCxR is zero
‘1’, if OCxR is non-zero
No interrupt
111 PWM with Fault Protection
‘0’, if OCxR is zero
‘1’, if OCxR is non-zero
OCFA falling edge for OC1 to OC4
FIGURE 14-2:
OUTPUT COMPARE OPERATION
Output Compare
Mode Enabled
Timer is Reset on
Period Match
OCxRS
TMRy
OCxR
Active-Low One-Shot
(OCM = 001)
Active-High One-Shot
(OCM = 010)
Toggle
(OCM = 011)
Delayed One-Shot
(OCM = 100)
Continuous Pulse
(OCM = 101)
PWM
(OCM = 110 or 111)
DS70318D-page 194
Preliminary
© 2009 Microchip Technology Inc.
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