DSPIC33FJ16GS204-I/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ16GS204-I/SP Datasheet PDF : 346 Pages
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER
HS/HC-0
FLTSTAT(1)
bit 15
HS/HC-0
CLSTAT(1)
HS/HC-0
TRGSTAT
R/W-0
FLTIEN
R/W-0
CLIEN
R/W-0
TRGIEN
R/W-0
ITB(3)
R/W-0
MDCS(3)
bit 8
R/W-0
R/W-0
U-0
DTC<1:0>
—
bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
CAM(2,3) XPRES(4)
IUE
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5-3
FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending
0 = No Fault interrupt is pending. This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending. This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending. This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt enabled
0 = Current-limit interrupt disabled and the CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit(3)
1 = PHASEx/SPHASEx register provides time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
MDCS: Master Duty Cycle Register Select bit(3)
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx/SDCx register provides duty cycle information for this PWM generator
DTC<1:0>: Dead-Time Control bits
00 = Positive dead time actively applied for all output modes
01 = Negative dead time actively applied for all output modes
10 = Dead-time function is disabled
11 = Reserved
Unimplemented: Read as ‘0’
Note 1: Software must clear the interrupt status here and the corresponding IFS bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
4: To operate in External Period Reset mode, configure FCLCONx<CLMOD> = 0 and PWMCONx<ITB> = 1.
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 203
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