DSPIC33FJ16GS204-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ16GS204-I/SP

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)

bit 2

CAM: Center-Aligned Mode Enable bit(2,3)

1 = Center-Aligned mode is enabled

0 = Center-Aligned mode is disabled

bit 1

XPRES: External PWM Reset Control bit(4)

1 = Current-limit source resets time base for this PWM generator if it is in Independent Time Base mode

0 = External pins do not affect PWM time base

bit 0

IUE: Immediate Update Enable bit

1 = Updates to the active MDC/PDCx/SDCx registers are immediate

0 = Updates to the active MDC/PDCx/SDCx registers are synchronized to the PWM time base

Note 1: Software must clear the interrupt status here and the corresponding IFS bit in the interrupt controller.

2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

4: To operate in External Period Reset mode, configure FCLCONx<CLMOD> = 0 and PWMCONx<ITB> = 1.

DS70318D-page 204

Preliminary

© 2009 Microchip Technology Inc.

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