dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
bit 15
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
AMSK<9:8>
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
AMSK<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSK<9:0>: Mask for Address bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match not required in this position
0 = Disable masking for bit x; bit match required in this position
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 229