DSPIC33FJ16GS102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ16GS102-I/SO

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

18.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

Note:

This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “dsPIC33F Family

Reference Manual”, Section 17. “UART”

(DS70188), which is available on the

Microchip web site (www.microchip.com).

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules

available in the dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 device families. The UART

is a full-duplex, asynchronous system that can

communicate with peripheral devices, such as

personal computers, LIN, RS-232 and RS-485

interfaces. The module also supports a hardware flow

control option with the UxCTS and UxRTS pins and

also includes an IrDA® encoder and decoder.

The primary features of the UART module are:

• Full-Duplex, 8-Bit or 9-Bit Data Transmission

through the UxTX and UxRX pins

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Hardware Flow Control Option with UxCTS and

UxRTS Pins

• Fully Integrated Baud Rate Generator with 16-Bit

Prescaler

• Baud Rates Ranging from 1 Mbps to 15 bps at

16x mode at 40 MIPS

• Baud Rates Ranging from 4 Mbps to 61 bps at

4x mode at 40 MIPS

• 4-Deep First-In First-Out (FIFO) Transmit Data

Buffer

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

• A Separate Interrupt for all UART Error Conditions

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Support for Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA® Support

A simplified block diagram of the UART module is

shown in Figure 18-1. The UART module consists of

these key hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 18-1:

UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA®

Hardware Flow Control

UART Receiver

UxRTS

UxCTS

UxRX

UART Transmitter

UxTX

© 2009 Microchip Technology Inc.

Preliminary

DS70318D-page 231

Share Link: