DSPIC33FJ16GS102-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC33FJ16GS102-I/SO

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

Section 7.0 “Oscillator

Configuration”

Removed the first sentence of the third clock source item (External Clock) in

Section 7.1.1 “System Clock sources”

Section 8.0 “Power-Saving

Features”

Section 9.0 “I/O Ports”

Updated the default bit values for DOZE and FRCDIV in the Clock Divisor

Register (see Register 7-2).

Added the following six registers:

• “PMD1: Peripheral Module Disable Control Register 1”

• “PMD2: Peripheral Module Disable Control Register 2”

• “PMD3: Peripheral Module Disable Control Register 3”

• “PMD4: Peripheral Module Disable Control Register 4”

• “PMD6: Peripheral Module Disable Control Register 6”

• “PMD7: Peripheral Module Disable Control Register 7”

Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain

Configuration”, which provides details on I/O pins and their functionality.

Removed 9.1.2 “5V Tolerance”.

Updated MUX range and removed virtual pin details in Figure 9-2.

Updated PWM Input Name descriptions in Table 9-1.

Added Section 9.4.2.3 “Virtual Pins”.

Updated bit values in all Peripheral Pin Select Input Registers (see

Register 9-1 through Register 9-14).

Updated bit name information for Peripheral Pin Select Output Registers

RPOR16 and RPOR17 (see Register 9-30 and Register 9-31).

Added the following two registers:

• “RPOR16: Peripheral Pin Select Output Register 16”

• “RPOR17: Peripheral Pin Select Output Register 17”

Section 14.0 “High-Speed PWM”

Removed the following sections:

• 9.4.2 “Available Peripherals”

• 9.4.3.2 “Virtual Input Pins”

• 9.4.3.4 “Peripheral Mapping”

• 9.4.5 “Considerations for Peripheral Pin Selection” (and all subsections)

Added Note 1 (remappable pin reference) to Figure 14-1.

Added Note 2 (Duty Cycle resolution) to PWM Master Duty Cycle Register

(Register 14-5), PWM Generator Duty Cycle Register (Register 14-7), and

PWM Secondary Duty Cycle Register (Register 14-8).

Section 15.0 “Serial Peripheral

Interface (SPI)”

Added Note 2 and Note 3 and updated bit information for CLSRC and

FLTSRC in the PWM Fault Current-Limit Control Register (Register 14-15).

Removed the following sections, which are now available in the related

section of the dsPIC33F Family Reference Manual:

• 15.1 “Interrupts”

• 15.2 “Receive Operations”

• 15.3 “Transmit Operations”

• 15.4 “SPI Setup” (retained Figure 15-1: SPI Module Block Diagram)

DS70318D-page 330

Preliminary

© 2009 Microchip Technology Inc.

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