dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 8.0 “Oscillator
Configuration”
Added Note 2 to the Oscillator System Diagram (see Figure 8-1).
Added a paragraph regarding FRC accuracy at the end of Section 8.1.1
“System Clock Sources”.
Added Note 1 and Note 2 to the OSCON register (see Register ).
Added Note 1 to the OSCTUN register (see Register 8-4).
Section 10.0 “I/O Ports”
Added Note 3 to Section 8.4.2 “Oscillator Switching Sequence”.
Removed Table 9-1 and added reference to pin diagrams for I/O pin
availability and functionality.
Added paragraph on ADPCFG register default values to Section 10.2
“Configuring Analog Port Pins”.
Section 15.0 “High-Speed PWM”
Added Note box regarding PPS functionality with input mapping to
Section 10.4.2.1 “Input Mapping”.
Updated Note 2 in the PTCON register (see Register 15-1).
Added Note 4 to the PWMCONx register (see Register 15-6).
Updated Notes for the PHASEx and SPHASEx registers (see Register 15-9
and Register 15-10, respectively).
Section 16.0 “Serial Peripheral
Interface (SPI)”
Added Note 2 and Note 3 to the SPIxCON1 register (see Register 16-2).
Section 18.0 “Universal
Updated the Notes in the UxMode register (see Register 18-1).
Asynchronous Receiver Transmitter
(UART)”
Updated the UTXINV bit settings in the UxSTA register and added Note 1
(see Register 18-2).
Section 19.0 “High-Speed 10-bit
Updated the SLOWCLK and ADCS<2:0> bit settings and updated Note 1in
Analog-to-Digital Converter (ADC)” the ADCON register (see Register 19-1).
Removed all notes in the ADPCFG register and replaced them with a single
note (see Register 19-4).
Updated the SWTRGx bit settings in the ADCPCx registers (see
Register 19-5, Register 19-6, Register 19-7, and Register 19-8).
DS70318D-page 334
Preliminary
© 2009 Microchip Technology Inc.