DSPIC30F2012AT-20E/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F2012AT-20E/ML

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC30F2011/2012/3012/3013

INDEX

Numerics

12-bit Analog-to-Digital Converter (A/D) Module .............. 111

A

A/D .................................................................................... 111

Aborting a Conversion .............................................. 113

ADCHS Register ....................................................... 111

ADCON1 Register..................................................... 111

ADCON2 Register..................................................... 111

ADCON3 Register..................................................... 111

ADCSSL Register ..................................................... 111

ADPCFG Register..................................................... 111

Configuring Analog Port Pins.............................. 60, 117

Connection Considerations....................................... 117

Conversion Operation ............................................... 112

Effects of a Reset...................................................... 116

Operation During CPU Idle Mode ............................. 116

Operation During CPU Sleep Mode.......................... 116

Output Formats ......................................................... 116

Power-Down Modes.................................................. 116

Programming the Sample Trigger............................. 113

Register Map............................................................. 119

Result Buffer ............................................................. 112

Sampling Requirements............................................ 115

Selecting the Conversion Sequence......................... 112

AC Characteristics ............................................................ 157

Load Conditions ........................................................ 157

AC Temperature and Voltage Specifications .................... 157

ADC

Selecting the Conversion Clock ................................ 113

ADC Conversion Speeds .................................................. 114

Address Generator Units .................................................... 43

Alternate Vector Table ........................................................ 69

Analog-to-Digital Converter. See ADC.

Assembler

MPASM Assembler................................................... 144

Automatic Clock Stretch...................................................... 98

During 10-bit Addressing (STREN = 1)....................... 98

During 7-bit Addressing (STREN = 1)......................... 98

Receive Mode ............................................................. 98

Transmit Mode ............................................................ 98

B

Bandgap Start-up Time

Requirements............................................................ 164

Timing Characteristics .............................................. 164

Barrel Shifter ....................................................................... 27

Bit-Reversed Addressing .................................................... 46

Example ...................................................................... 47

Implementation ........................................................... 46

Modifier Values Table ................................................. 47

Sequence Table (16-Entry)......................................... 47

Block Diagrams

12-bit ADC Functional............................................... 111

16-bit Timer1 Module .................................................. 73

16-bit Timer2............................................................... 79

16-bit Timer3............................................................... 79

32-bit Timer2/3............................................................ 78

DSP Engine ................................................................ 24

dsPIC30F2011 ............................................................ 12

dsPIC30F2012 ............................................................ 13

dsPIC30F3013 ............................................................ 15

External Power-on Reset Circuit............................... 129

I2C .............................................................................. 96

Input Capture Mode.................................................... 83

Oscillator System...................................................... 123

Output Compare Mode ............................................... 87

Reset System ........................................................... 127

Shared Port Structure................................................. 59

SPI.............................................................................. 91

SPI Master/Slave Connection..................................... 92

UART Receiver......................................................... 104

UART Transmitter..................................................... 103

BOR Characteristics ......................................................... 155

BOR. See Brown-out Reset.

Brown-out Reset

Characteristics.......................................................... 155

Timing Requirements ............................................... 163

C

C Compilers

MPLAB C18.............................................................. 144

MPLAB C30.............................................................. 144

CAN Module

I/O Timing Characteristics ........................................ 179

I/O Timing Requirements.......................................... 179

CLKOUT and I/O Timing

Characteristics.......................................................... 162

Requirements ........................................................... 162

Code Examples

Data EEPROM Block Erase ....................................... 56

Data EEPROM Block Write ........................................ 58

Data EEPROM Read.................................................. 55

Data EEPROM Word Erase ....................................... 56

Data EEPROM Word Write ........................................ 57

Erasing a Row of Program Memory ........................... 51

Initiating a Programming Sequence ........................... 52

Loading Write Latches................................................ 52

Code Protection ................................................................ 121

Control Registers ................................................................ 50

NVMADR .................................................................... 50

NVMADRU ................................................................. 50

NVMCON.................................................................... 50

NVMKEY .................................................................... 50

Core Architecture

Overview..................................................................... 19

CPU Architecture Overview ................................................ 19

Customer Change Notification Service............................. 200

Customer Notification Service .......................................... 200

Customer Support............................................................. 200

D

Data Accumulators and Adder/Subtractor .......................... 25

Data Space Write Saturation ...................................... 27

Overflow and Saturation ............................................. 25

Round Logic ............................................................... 26

Write-Back .................................................................. 26

Data Address Space........................................................... 35

Alignment.................................................................... 38

Alignment (Figure) ...................................................... 38

Effect of Invalid Memory Accesses (Table) ................ 38

MCU and DSP (MAC Class) Instructions Example .... 37

Memory Map......................................................... 35, 36

Near Data Space ........................................................ 39

Software Stack ........................................................... 39

Spaces........................................................................ 38

Width .......................................................................... 38

Data EEPROM Memory...................................................... 55

Erasing ....................................................................... 56

© 2008 Microchip Technology Inc.

DS70139F-page 197

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